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STW5094
18 BIT 8kHz TO 48kHz LOW POWER STEREO AUDIO DAC WITH INTEGRATED POWER AMPLIFIERS AND VOICE CODEC
FEATURES: Complete STEREO AUDIO DAC and FILTERS including: s 18 BIT DIGITAL TO ANALOG CONVERTERS. s LINEAR PHASE DIGITAL FILTERS. s ACTIVE LINEAR PHASE SMOOTHING FILTER. s 30 LOAD STEREO HEADPHONES DRIVERS, 8 LOAD MONO LOUDSPEAKER DRIVER FOR GROUP LISTENING. Stereo Audio DAC Features: s MULTIBIT MODULATOR WITH DATA WEIGHTED AVERAGING DAC. s 92 dB DYNAMIC RANGE, 0.01% THD OVER 30 LOAD PERFORMANCE. s SUPPORTS ALL THE MPEG 1 & 2 SAMPLING FREQUENCIES AND THE EXTENSION TO MPEG 2.5: 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, 48 kHz. s TONES FROM TONE GENERATOR CAN BE INJECTED IN THE AUDIO PATHS. Stereo Headphones and Loudspeaker/Earpiece Power Amplifiers features and Stereo Input for FM Radio Features: s 20kHz BANDWIDTH STEREO HEADPHONES OUTPUTS. DRIVING CAPABILITY: 20mW (TYP. 0.1% T.H.D) OVER 30 WITH 40 dB RANGE PROGRAMMABLE GAIN. s BALANCED EARPIECE LOUDSPEAKER OUTPUT. DRIVING CAPABILITY: 190mW (TYP. 0.1% T.H.D) OVER 8 WITH 30dB RANGE PROGRAMMABLE GAIN. s ANALOG STEREO INPUT FOR FM RADIO WITH 38 dB RANGE PROGRAMMABLE GAIN. Complete CODEC and FILTER system including: s 14 BIT LINEAR ADC AND DAC. s 8 BIT COMPANDED ADC AND DAC A-LAW OR -LAW. s TRANSMIT AND RECEIVE DIGITAL BAND-PASS FILTERS. s ACTIVE ANTIALIAS AND SMOOTHING FILTERS. s 8 LOAD EARPIECE/LOUDSPEAKER DRIVER, 30 LOAD AUXILIARY DRIVER.
November 2003
TFBGA 6x6 (36 pins) ORDERING NUMBER: STW5094
Voice CODEC Features: s SUPPORT BOTH 8kHz AND 16kHz SAMPLING RATE. s ONE MICROPHONE BIASING OUTPUT. s REMOTE CONTROL FUNCTION. s ONE LINE INPUT AND TWO SWITCHABLE MICROPHONE AMPLIFIER INPUTS. 42.5dB RANGE PROGRAMMABLE GAIN. s TRANSIENT SUPRESSION DURING POWER UP AND POWER DOWN. s INTERNAL PROGRAMMABLE SIDETONE CIRCUIT. s INTERNAL RING, TONE AND DTMF GENERATOR. s PROGRAMMABLE PWM BUZZER DRIVER. General Features: s SINGLE 2.7V to 3.3V SUPPLY. s EXTENDED TEMPERATURE RANGE OPERATION (*) -40C to 85C. s 1 W STANDBY POWER (TYP. AT 2.7V). s 13 mW OPERATING POWER IN AUDIO LISTENING MODE (TYP. AT 2.7V). s 11 mW OPERATING POWER IN VOICE CODEC MODE (TYP. AT 2.7V). s 1.8V TO 3.3V CMOS COMPATIBLE DIGITAL INTERFACES. s PROGRAMMABLE PCM INTERFACE. 2 s I C COMPATIBLE CONTROL INTERFACE. s PROGRAMMABLE SERIAL AUDIO DATA INPUT INTERFACE (I2S AND OTHER FORMATS).
(*) Functionality guaranteed in the range - 40C to +85C; Timing and Electrical Specifications are guaranteed in the range - 30C to +85C.
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APPLICATIONS: s CDMA,GSM,DCS1800,PCS1900,JDC DIGITAL CELLULAR TELEPHONES WITH MP3 AND FM RADIO STEREO LISTENING FUNCTIONS. s PORTABLE DEVICES WITH A STEREO DIGITAL AUDIO SOURCE AND FM RADIO LISTENING FUNCTION. GENERAL DESCRIPTION STW5094 is a low power Stereo Audio DAC device with Headphones Amplifiers for high quality MP3 and FM radio listening. The STW5094 includes also an high performance low power combined PCM CODEC FILTER tailored to implement the audio front-end functions required by low voltage low power consumption digital cellular terminals with added MP3 and FM radio listening. STW5094 offers a number of programmable functions accessed through an I2C-bus compatible interface. The STW5094 Stereo Audio DAC section is suited for MP3, or any other audio stereo source, listening. It supports all the MP3 rates from 8kHz to 48kHz. The audio data serial interface is I2S compatible and can be programmed to handle 16 to 24 bit word length input data. The internal D to A converters work with 18 bit input resolution. PIN CONNECTIONS (Top view) 1
MIC2N
The Stereo Headphones drivers can also be used for FM Radio listening via an auxiliary stereo analog input. A Loudspeaker driver can also be used for monophonic group listening. The STW5094 Voice Codec section can be configured either as a 14-bit linear or as an 8-bit companded PCM coder. The Frame Synchronism frequency of the Voice Codec can be either the standard 8kHz value or the extended 16kHz one. In addition to the Stereo Audio DAC and CODEC FILTER functions, STW5094 includes a Tone Ring DTMF generator that can be used both in Audio Listening mode and in Voice Codec mode, a sidetone generation, a buzzer driver output and a remote control function tailored to handle an external on-hook off-hook button. STW5094 Voice Codec fulfills and exceeds D3 D4 and CCITT recommendations and ETSI requirements for digital handset terminals. The Stereo Audio DAC part fulfills and exceeds the requirements for MP3 quality and FM radio quality listening. Main applications include digital mobile phones, as cellular and cordless phones, with added low-power high-quality MP3 and or FM radio listening features, or any battery powered equipment that requires Stereo Audio DAC with Headphones drivers operating at low single supply voltage.
2
3
4
MCLK
5
DR
6
DX
MIC2P REMOUT
A
MIC1P MIC1N MBIAS VCC FS GND
B
MIC3 VCCA CAP2 REMIN AUXCLK LRCK
C
GNDA FMR GNDCM VCCIO SDI SCK
D
FML HPL GNDP DNC OCK BZ
E
LSN LSP VCCP HPR SDA SCL
F
TFBGA 6x6x1.2 (36 Pin)
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VCCA
GNDA
VCCP
GNDP
GNDCM
VCC
GND
VCCIO
MIC1P AUXCLK 0:22.5 dB
AUX CK Gen
MIC1N
MIC2P 0/20dB Gain. DE Remocon ADC Voice PreAmp Anti Alias Filter TX Channel Filter
MIC2N
REMOUT REMIN 0:-27 dB Tone Generator -12:-27 dB Tone Att.
FUNCTIONAL BLOCK DIAGRAM
MIC3
BZ
Buzzer
MCLK
MBIAS SI
Bandgap
Mic. Bias
VCM
SideTone Gain PCM I/F
FS
CAP2
Voice Mode FM Mode Analog Filter DAC
DX
+18:-20 dB Step 2 RX Channel Filter DR
FML
FML PreAmp
+18:-20 dB Step 2
FMR On Reset
Power
FMR PreAmp
Control Logic
Registers
I2C
I/F
SDA
SCL
0:-40 dB FME OS SE Audio Mode Analog Filter RTE Voice Mode
Transient
Mute
HPL
Left Driver
Suppression Filter
DAC
Modulator
Interpolation Filter
LRCK
+6:-24 dB
LSP
Diff Driver Voice Mode
Transient I2S
I/F RTE SE
LSN FME OS
Suppression Filter
SDI
0:-40 dB
SCK
Transient
Mute
HPR
Right Driver
NOTE: This diagram shows the functionality of the device and of some register bits but it does not necessarily reflect the exact hardware implementation
OCK Audio Mode Analog Filter DAC Modulator Interpolation Filter
Suppression Filter
STW5094
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PIN FUNCTION
Pin N B1 B2 A2 A1 C1 B3 E1 D2 F2,F1 Name MIC1P MIC1N MIC2P MIC2N MIC3 MBIAS FML FMR LSP, LSN Type AI AI AI AI AI AO AI AI AO Description Positive high impedance input to transmit preamplifier for microphone 1 connection. Negative high impedance input to transmit preamplifier for microphone 1 connection. Positive high impedance input to transmit preamplifier for microphone 2 connection. Negative high impedance input to transmit preamplifier for microphone 2 connection. High impedance single ended input to transmit preamplifier for line input connection. Only 0dB gain is allowed. Microphone Biasing Switch. Auxiliary analog audio Left channel input. Auxiliary analog audio Right channel input. Receive analog amplifier complementary outputs. This differential output can drive 50nF (with series resistor) or directly an earpiece transductor of 8. The signal at this output can be: the sum of the Receive Speech signal from DR, the Internal Tone Generator, and the Sidetone signal, or the sum of the Audio Left channel and the Internal Tone Generator, or can come from FML input. Audio headphone amplifier Left channel output. This output can drive 50nF (with series resistor) or directly an earpiece transductor of 30. The signal at this output can be the sum of Audio Left channel and Internal Tone Generator, or the sum of Receive Speech signal from DR, Internal Tone Generator, Sidetone signal, or can come from FML input. Audio headphone amplifier Right channel output. This output can drive 50nF (with series resistor) or directly an earpiece transductor of 30. The signal at this output can be the sum of Audio Right channel and Internal Tone Generator, or the sum of Receive Speech signal from DR, Internal Tone Generator, Sidetone signal, or can come from FMR input. Remocon function digital output. Remocon function input. A high level at this pin is detected as a non pressed key, while a low level is detected as a pressed key. Pulse width modulated buzzer driver output. I2C-bus interface serial clock input. SCL is asynchronous with the other system clocks. I2C-bus interface serial data input-output. Left Right clock for Audio interface input. Audio interface Clock input. Audio interface Data input. Master Clock Input for Audio Mode. Can also be used as Master Clock in Tone Only and FM Modes. Transmit Data output: Data is shifted out on this pin during the assigned transmit time slots. Elsewhere DX output is in the high impedance state. In delayed and non-delayed normal frame sync modes, voice data byte is shifted out from tristate output DX at the MCLK frequency on the rising edge of MCLK, while in non-delayed reverse frame sync mode voice data is shifted out on the falling edge of MCLK. Receive data input: Data is shifted in during the assigned Received time slots In delayed and non-delayed normal frame sync modes voice data byte is shifted in at the MCLK frequency on the falling edges of MCLK, while in non-delayed reverse frame sync mode voice data byte is shifted in on the rising edge of MCLK.
E2
HPL
AO
F4
HPR
AO
A3 C4 E6 F6 F5 C6 D6 D5 E5 A6
REMOUT REMIN BZ SCL SDA LRCK SCK SDI OCK DX
DO DI AO DI DIO DI DI DI DI DOT
A5
DR
DI
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PIN FUNCTION (continued)
Pin N B5 Name FS Type DI Description Frame Sync input: This signal is a 8 16kHz clock which defines the start of the transmit and receive frames. Any of three formats may be used for this signal: non delayed normal mode, delayed mode, and non delayed reverse mode. Master Clock Input for Voice Mode. Can also be used as Master Clock in Tone Only and FM Modes. The allowed clock frequencies are 512 kHz, 1.536 MHz, 2.048 MHz or 2.56 MHz. MCLK is the Voice Data Clock. Auxiliary Clock Input. Can be used as Master Clock in Tone Only and FM Modes. Allowed clock frequencies are 512kHz, 1.536MHz, 2.048MHz or 2.56MHz. Do Not Connect. This pin must be left unconnected. A capacitor must be connected between this node and Ground. Power supply input for the analog section. VCC and VCCA can be directly connected together for low cost applications. Analog Ground: All analog signals are referenced to this pin. GND and GNDA can be connected together for low cost applications. Power supply input for the output drivers. VCCP and VCCA must be connected together. Power ground. Output drivers are referenced to this pin. GNDP and GNDA must be connected together. Analog Ground connection. GNDCM can be connected to GNDA. Power supply input for the digital section. Ground for the digital section Power supply Input for the Digital I O pins.
A4
MCLK
DI
C5 E4 C3 C2 D1 F3 E3 D3 B4 B6 D4
AUXCLK DNC CAP2 VCCA GNDA VCCP GNDP GNDCM VCC GND VCCIO
DI AI AI P P P P P P P P
Type definitions: AI - Analog input, AO - Analog Output, DI - Digital Input, DO - Digital output, DOT - Digital Output Tristate, DIO - Digital Input Output Open Drain, P - Power Supply or Ground.
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FUNCTIONAL DESCRIPTION I DEVICE MODES STW5094 can work in 4 different modes, selected by bits MD in Control Register 18 (CR18). Depending on the mode different data interfaces, clock inputs, and internal blocks are selected. A built-in power consumption management function keeps in power down the blocks that are not needed by the selected operating mode. In all the modes the Output Drivers can be activated in all the combinations allowed by bits OS in CR6 (in case of stereo input and LSP N driver selected the Left channel is sent to this driver, while in case of voice input and HPL + HPR drivers selected the same signal is sent to both drivers). I.1 Audio Mode: In Audio mode the path from the I2S I F to the output drivers is active to allow the Stereo Audio DAC function. The I2S I F is active while the PCM I F is inactive. The master clock of the device is OCK. The OCK frequency must be 256 times the sampling frequency for the MPEG1 and MPEG2 sampling frequencies and 512 times for the MPEG2.5 sampling frequencies. The sampling frequency (LRCK frequency) can be selected with bits LAY and AFS in REG6. Since the OCK clock is used directly in all the Audio blocks, its jitter and spectral properties must be adequate to the desired Audio quality. The Tone Ring DTMF generator can be activated if needed. The FM preamplifiers are in power down. I.2 Voice Mode: In Voice mode the TX path from microphone or line input to DX and the RX path from DR to the output drivers are active to allow the PCM CODEC function. The PCM I F is active while the I2S I F is inactive. The master clock of the device is MCLK, the frequency of the clock can be selected with bits F in CR0. The FM preamplifiers are in power down. I.3 Tone Only Mode: In Tone Only mode the path from the Tone generator to the output Drivers and to the Buzzer is active to allow Tones or Ringer listening only. Both I2S I F and PCM I F are inactive, as all the Audio and Voice converters functions. The master clock of the device can be selected to be AUXCLK, MCLK or OCK (bits CFM in CR18). The Tone Ring DTMF generator can be activated if needed. The FM preamplifiers are in power down. I.4 FM Mode: In FM mode the path from FML and FMR analog inputs to the output Drivers is active to allow FM Stereo Radio listening. Both I2S I F and PCM I F are inactive, as all the Audio and Voice converters functions. The master clock of the device can be selected to be AUXCLK, MCLK or OCK (bits CFM in CR18). The Tone Ring DTMF generator is in power down.
II DEVICE OPERATION II.1 Power on initialization and Software Reset: When power is first applied, power on reset circuitry initializes STW5094 and puts it into the power down state. All the Registers are initialized as indicated in the Control Register description section. All the functions are disabled. The registers can be initialized also writing bit SRS (software reset) in CR18.
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II.2 Power up down control: It is recommended that all programmable functions (excluding the gain controls) are set while the device is powered down. Power state control can then be included in the last programming instruction (the power up bit PU is located in the last address register (CR18) so that the multi-byte mode of the control interface can be easily used to program all the required functions before power up). When a power up command is given, all the circuits needed for the selected mode are activated (in Voice mode the DX output will remain in the high impedance state until the second FS pulse after power up arrives). A built-in power consumption management function keeps in power down the blocks that are not needed by the selected operating mode. II.3 Power down state: Following a period of activity, power down state may be reentered by writing 0 in bit PU in CR18. All the Control Registers remain in their current state and can be changed by I2C control interface. In addition to the power down instruction, the detection of absence of the current Master Clock (no transition detected) automatically puts the device in power down state without setting bit PU. If transitions on the master clock are detected the device is put again in power up. II.4 Voice Transmit section: This section is active in Voice Mode. Voice Transmit analog preamplifier gain is designed in two stages to enable gains up to 42.5 dB. Stage 1 provides a selectable 0 or 20 dB gain via bit PG in CR4. Stage 2 is a programmable gain amplifier which provides from 0 to 22.5 dB of additional gain in 1.5dB step. It can be programmed with bits TXA in CR4. Two differential microphone inputs (MIC1P N, MIC2P N) and one single ended line input (MIC3) are provided. The line input MIC3 can only be used with preamplifier gain set to 0dB in both stages. The microphone input or Transmit Mute is selected with bits MS in CR4. In the Mute case, the analog transmit signal is grounded. A separate MBIAS output can be used to bias a microphone (bit MB in CR4). An active anti-alias filter then precedes the single bit analog to digital converter that is followed by an 8th order IIR digital TX channel filter. The TX channel filter is band-pass if the FS frequency is 8kHz and low-pass if the FS frequency is 16kHz (bit VFS in CR0). A precision on chip voltage reference ensures accurate and highly stable transmission levels. Any offset voltage arising in the analog blocks is cancelled by an internal autozero circuit. Voice data is sent to the PCM I F to be serially sent to DX output. II.5 Voice Receive section: This section is active in Voice Mode. Voice Data coming from PCM I F DR pin is sent to the 8th order digital IIR RX channel filter. The filter can be selected to be band-pass or low-pass, with bit HPB in CR5, when FS frequency is 8kHz, while it is always low-pass when FS frequency is 16kHz. The filter is followed by a digital to analog converter and a 3rd order switched-capacitor reconstruction filter. The Sidetone can be summed to the received signal (bit SI in CR5) and its amplitude can be programmed with bits SA in CR5. II.6 Stereo Audio DAC section: This section is active in Audio Mode. The Left and Right Audio samples coming from the I2S Interface are interpolated with an FIR filter in order to feed the oversampled multi-bit modulator, the digital to analog converter is followed by a 3rd order switched-capacitor reconstruction filter. II.7 Output Drivers section: There are 3 Analog Output Drivers. The LSP N differential driver delivers 190mW typical power with 0.1% T.H.D. (140mW minimum undistorted) on a 8 earpiece loudspeaker (piezoceramic loads up to 50nF can also be driven, with a series resistor), it has a 30dB range gain control (bits LSA in CR7). The 2 single ended drivers (HPL and HPR) deliver 20mW typical power with 0.1% T.H.D. (16.5mW minimum undistorted) on 30 stereo headphones, they have a 40dB range gain control (CR8 for HPL and CR9 for HPR). It is possible to put all the drivers in power-down, enable the LSP N one, enable the HPL one or enable HPL and HPR together
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programming bits OS in CR6. These settings are not dependent from the selected operative Mode. If HPL and HPR are enabled together in Voice Mode or Tone Only Mode the same signal is sent to both Drivers. The active Drivers can be muted (keeping them in power-up state) using bit MUT in CR7. At power-up or after a change in OS bits the outputs are muted for 10 ms to avoid unwanted noise. The transient suppression filter is used to avoid clicks when the gain value is changed. II.8 Tone Generator: The Tone Generator can be activated (writing CR12) in all the STW5094 operating modes except FM mode. In Voice and Audio modes the tones are summed to the signal. It is possible to generate 1 or 2 summed waveforms (either sinusoidal or square wave), their frequencies can be set in CR13 for the first one (f1) and in CR14 for the second one (f2) accordingly to the values listed in Table 1. The amplitude of the generated waveform can be regulated in CR12 over a 33dB range. When both f1 and f2 are selected the amplitude of f1 and f2 are lowered by 5dB and 7dB respectively with respect to the amplitude of a single waveform. In this way the amplitude of the summed waveforms does not overload and there is a 2dB difference between f1 and f2 amplitude as required for DTMF generation. The Tone Generator output can be sent to the Voice Transmit section (in Voice Mode), to the Power amplifiers, possibly mixed with audio or voice, (in all the modes except FM mode) and to the buzzer output BZ (in all the modes except FM mode). II.9 Buzzer Output: The output BZ is intended to drive a Buzzer, via an external BJT, with a squarewave pulse width modulated (PWM) signal. The frequency of the signal is stored in CR13 (see Table1 for frequency values). For some applications it is also possible to multiply this PWM signal with a squarewave signal having a frequency stored in CR14. The duty cycle of the buzzer output can be varied in CR15 in order to change the buzzer volume. Maximum load for BZ is 5k and 50pF. II.10 Voice Data Interface (PCM I F): The PCM I F is used to exchange the Voice data in both TX and RX direction, it can be programmed for linear format data or companded A-law or -law format (see Fig.1, 2 and 3). Frame Sync input FS determines the beginning of frame. It may have any duration from a single cycle of MCLK to a squarewave. Three different relationships may be established between the Frame Sync input and the first time slot of the frame by setting bits DM in CR1. In non delayed normal and reverse data mode (long frame timing) the first time slot starts at the rising edge of FS. In delayed data mode (short frame sync timing) FS input must be high for at least a half cycle of MCLK before the frame start. When linear code is selected (bit CM = 0 in CR0) the MSB is transmitted and received first, the word length is 16 bit. When companded code is selected (bit CM = 1 in CR0) a time slot assignment may be used in all timing modes (bit TS in CR1), that allows connection to one of the two B1 and B2 voice data channels. Two data formats are available: in Format 1, time slot B1 corresponds to the 8 MCLK cycles that immediately follow the rising edge of FS, while time slot B2 corresponds to the 8 MCLK cycles that immediately follow time slot B1. In Format 2, time slot B1 is identical to Format 1 while time slot B2 appears two bit slots after time slot B1. This two bits space is left available for insertion of the D channel data. Data format is selected by bit FF in CR0. Bit EN in CR1 enables or disables data transfer on DX and DR. Outside the selected time slot DX is in the high impedance condition. During the selected time slot the DX output and the DR input are synchronized as follow: -If delayed or non-delayed modes are selected the transmit voice data is sent to DX output on the rising edges of MCLK and receive voice data is read at DR input on the falling edges of MCLK. -If non-delayed reverse mode is selected the transmit voice data register is sent to DX output on the falling edges of MCLK and receive voice data is read at DR input on the rising edges of MCLK. When 16kHz Frame Sync frequency is selected (bit VFS in CR0) the RX and TX filters are both low-pass and their cutoff frequencies are doubled. It is possible to access the B channel data when companded A-law or -law formats are used (bits MX and MR in CR1). A byte written into CR3 will be sent to DX output in place of the transmit channel PCM data. A byte written in CR2 will be sent to the receive path. The current byte received on DR input can be read in CR2.
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II.11 Audio Data Interface (I2S I F): The I2S I F is used to receive the Left and Right channel Audio data (see Fig. 4 and 5). The interface is I2S compatible and can be configured in other different modes writing CR16. When the I2S I F is active (Audio mode) the Master Clock of the device is OCK. The frequency of OCK is 256 times the sampling frequency (LRCK frequency) when the sampling frequency is between 16kHz and 48kHz (LAY(1) = 0 in CR6), and 512 times when the sampling frequency is between 8kHz and 12kHz (LAY = 10 in CR6). The polarity of OCK can be selected. SCK frequency is 32 times the LRCK one in case of 16bit Data word and 64 times in case of 18bit to 24bit Data word. Left channel data are always received first, the polarity of LRCK can be selected. The first 35 Data frames after power up are discarded while the interpolation filters data memory is cleared. II.12 Control Interface (I2C I F): The I2C I F is used to program the device by writing and reading the control registers (see Fig 6 and 7). The interface is I2C bus compatible, being the STW5094 a Slave device. SDA is the bidirectional open-drain data pin and SCL is the input clock pin. The Device Address is E2 hex. for writing and E3 hex. for reading. The interface has an internal address register that keeps the current address of the control register to be read or written. At each write access of the interface the address register is loaded with the data of the register address field. The value in the address register is increased after each data byte read or write. It is possible to access the interface in 2 modes: single-byte mode in which the address and data of a single register are specified, and multi-byte mode in which the address of the first register to be written or read is specified and all the following bytes exchanged are the data of successive address registers starting from the one specified (in multi-byte mode the internal address counter restart from register 0 after the last register 18). Using the multi-byte mode it is possible to write or read all the registers with a single access to the device on the I2C bus. The Control interface can be used both in power-up and power-down state. II.13 Master Clock in FM mode and Tone Only modes: In FM mode and in Tone Only mode the Master Clock of the device can be selected to be AUXCLK, MCLK or OCK writing bits CFM in CR18. The Auxiliary clock AUXCLK can be used when the Audio mode clock OCK and the Voice mode clock MCLK are not available. AUXCLK and MCLK frequency selection is done with bits F in CR0. II.14 REMOCON function: The REMOCON (Remote Control) function can be used to detect the status of an headset button. The REMOCON function is enabled by setting bit REN in CR17. If enabled, this function is active also when the STW5094 is in power-down state. A High level at REMIN input is detected as a non pressed button, while a low level is detected as a pressed button. The "Pressed Button" information can be treated in 2 ways depending on bit RLM in CR17: - if RLM = 0 (Transparent mode) the information at REMIN is seen at REMOUT after a debounce time of 50ms maximum; - if RLM = 1 (Latched Mode) the information stored in bit RDL in CR17 is seen at REMOUT. RDL is set after a debounce time of 50ms maximum when a low level at REMIN is detected. RDL is reset with power on initialization and can also be reset writing 0 in bit RDL. The REMOUT output polarity can be inverted setting bit ROI in CR17: the pressed button information is presented at REMOUT output as a logic 1 if bit ROI = 0. If ROI = 1 the polarity is inverted.
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III PROGRAMMABLE REGISTERS Control Register CR0 Functions (Address: 0x00)
7 6 5 VFS 4 CM 3 MA 2 IA 1 FF 0 Function F(1:0) 0 0 1 1 0 1 0 1 0 1 0 1 B7 MCLK or AUXCLK MCLK or AUXCLK MCLK or AUXCLK MCLK or AUXCLK = 512 kHz = 1.536 MHz = 2.048 MHz = 2.560 MHz *
Voice Data Fs is 8 kHz Voice Data Fs is 16 kHz Linear code Companded code Linear Code 0 0 1 1 0 1 0 1 0 1 0 1 2-complement * sign and magnitude 2-complement 1-complement B1 and B2 consecutive B1 and B2 separated 8 bits time-slot 7 bits time-slot Companded Code
* *
-law: CCITT D3-D4 * -law: Bare Coding A-law including even bit inversion A-law: Bare Coding (1) * (1) (1) * (1)
(1): significant in companded mode only *: state at power on initialization
Control Register CR1 Functions (Address: 0x01)
7 6 5 4 MR 3 MX 2 EN 1 TS 0 Function DM(1:0) 0 1 1 X 0 1 X 0 1 0 1 0 1 0 1 0 1
(1) significant in companded mode only *: state at power on initialization X: reserved: write 0
DL delayed data timing non-delayed normal data timing non-delayed reverse data timing *
DR connected to RX path CR2 connected to RX path TX path connected to DX CR3 connected to DX PCM I/F disabled PCM I/F enabled B1 channel selected B2 channel selected Normal operation Digital Loopback
* (1) * (1) * * (1) *
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Control Register CR2 Functions (Address: 0x02)
7 6 5 4 3 2 1 0 Function DRD(7:0) msb
(1) Significant in companded mode only.
lsb
Data sent to Receive path or Data received from DR input (1)
Control Register CR3 Functions (Address: 0x03)
7 6 5 4 3 2 1 0 Function DXD(7:0) msb
(1) Significant in companded mode only.
lsb
DX data transmitted (1)
Control Register CR4 Functions (Address: 0x04)
7 6 5 MB 4 PG 3 2 1 0 Function MS(1:0) 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 0 0 1 0 0 1 0 1 1 TXA(3:0) Transmit input muted MIC1 Selected MIC2 Selected MIC3 Selected MBIAS output disabled MBIAS output enabled 20dB preamplifier gain 0dB preamplifier gain 0 dB Transmit Amplifier gain 1.5 dB Transmit Amplifier gain Transmit Amplifier in 1.5 dB step 22.5 dB Transmit Amplifier gain *
(1) * * (1) (1)*
*: state at power on initialization (1) When the single ended line input MIC3 is selected, microphone gain must be set to 0dB (PG=1, TXA=0000).
Control Register CR5 Functions (Address: 0x05)
7 6 5 HPB X X 0 1 0 1 0 0 1 0 0 1 0 0 1 0 1 1 Voice Codec Receive High Pass filter enabled Voice Codec Receive High Pass filter disabled Voice Codec internal sidetone disabled Voice Codec internal sidetone enabled -12.5 dB Sidetone -13.5 dB Sidetone Sidetone gain in 1 -27.5 dB Sidetone gain gain dB step gain (1) * * * 4 SI 3 2 1 0 Function
SA(3:0)
*: state at power on initialization X: reserved: write 0 (1): Valid only when Voice Data Fs=8kHz (VFS=0). When Voice data Fs=16kHz (VFS=1) The High Pass Filter is always disabled.
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STW5094
Control Register CR6 Functions (Address: 0x06)
7 6 5 4 3 2 1 SE 0 Function LAY(1:0) 0 0 1 0 1 X 0 0 1 0 1 X 0 0 1 1 0 1 0 1 0 1 0 1 AFS(1:0) OS(1:0) RTE Audio Data Fs is 32 or 44.1 or 48 kHz Audio Data Fs is 16 or 22.025 or 24 kHz. Audio Data Fs is 8 or 11.025 or 12 kHz. Audio Data Fs is 44.1 or 22.05 or 11.025 kHz Audio Data Fs is 48 or 24 or 12 kHz. Audio Data Fs is 32 or 16 or 8 kHz. Output Drivers off LSP N output Driver selected. HPL output Driver selected. HPL and HPR output Drivers selected. Audio or Voice Codec Signal to LS or HP disabled Audio or Voice Codec Signal to LS or HP enabled. Ring Tone to LS or HP disabled Ring Tone to LS or HP enabled. (1) * (1) (2) *
*
* *
(1): OCK frequency must be 256 times Audio Data Fs frequency. (2): OCK frequency must be 512 times Audio Data Fs frequency. *: state at power on initialization X: reserved: write 0
Control Register CR7 Functions (Address: 0x07)
7 6 5 4 MUT X X X 0 1 0 0 1
*: state at power on initialization X: reserved: write 0
3
2
1
0 Function
LSA(3:0)
The selected output Drivers are operative The selected output Drivers are muted 0 0 1 0 0 1 0 1 1 Earpiece Earpiece Earpiece Earpiece Loudspeaker Amplifier 6 dB gain Loudspeaker Amplifier 4 dB gain Loudspeaker Amplifier gain in 2 dB step Loudspeaker Amplifier -24 dB gain
* *
Control Register CR8 Functions (Address: 0x08)
7 6 5 4 3 2 HPLA(4:0) X X X 0 0 1
*: state at power on initialization X: reserved: write 0
1
0 Function
0 0 0
0 0 1
0 0 0
0 1 0
Headphones amplifier (Left channel) 0 dB gain Headphones amplifier (Left channel) -2 dB gain Headphones amplifier (Left channel) gain in 2 dB step Headphones amplifier (Left channel) -40 dB gain
*
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STW5094
Control Register CR9 Functions (Address: 0x09)
7 6 5 4 3 2 HPRA(4:0) X X X 0 0 1
*: state at power on initialization X: write 0
1
0 Function
0 0 0
0 0 1
0 0 0
0 1 0
Headphones amplifier (Right Headphones amplifier (Right Headphones amplifier (Right Headphones amplifier (Right
channel) 0 dB gain * channel) -2 dB gain channel) gain in 2 dB step channel) -40 dB gain
Control Register CR10 Functions (Address: 0x0A)
7 6 5 4 3 2 FMLA(4:0) X X X 0 0 1
*: state at power on initialization X: reserved: write 0
1
0 Function
0 0 0
0 0 0
0 0 1
0 1 1
FM Preamplifier (Left channel) +18 dB gain FM Preamplifier (Left channel) +16 dB gain FM Preamplifier (Left channel) gain in 2 dB step FM Preamplifier (Left channel) -20 dB gain
*
Control Register CR11 Functions (Address: 0x0B)
7 6 5 4 3 2 FMRA(4:0) X X X 0 0 1
*: state at power on initialization X: reserved: write 0
1
0
Function
0 0 0
0 0 0
0 0 1
0 1 1
FM Preamplifier (Right FM Preamplifier (Right FM Preamplifier (Right FM Preamplifier (Right
channel) +18 dB gain channel) +16 dB gain channel) gain in 2 dB step channel) -20 dB gain
*
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STW5094
Control Register CR12 Functions (Address: 0x0C)
7 6 5 4 3 2 1 SN 0 DE Tone gain Tone gain Tone gain Tone gain 0 0 1 1 0 1 0 1 0 1 0 1
*: state at power on initialization X: reserved write 0
Function
TONEG(3:0) 0 0 1 0 0 0 0 0 1 0 1 1
FSEL(1:0)
is 0 dB is -3 dB in 3 dB step is -33 dB
*
f1 f1 f2 f1
and f2 muted selected selected and f2 in summed mode
*
Squarewave signal selected Sinewave signal selected Tone Ring Generator not connected to Transmit path Tone Ring Generator connected to Transmit path
* *
Control Register CR13 Functions (Address: 0x0D)
7 6 5 4 3 2 1 0 Function F1(7:0) msb lsb Binary equivalent of the decimal number used to calculate f1 See Table 1
Control Register CR14 Functions (Address: 0x0E)
7 6 5 4 3 2 1 0 Function F2(7:0) msb lsb Binary equivalent of the decimal number used to calculate f2 See Table 1
Control Register CR15 Functions (Address: 0x0F)
7 BE 0 1 0 1 msb lsb 6 BI 5 4 3 2 1 0 Function BZ(5:0) Buzzer output disabled (set to 0) Buzzer output enabled Duty Cycle is intended as the relative width of logic 1 Duty cycle is intended as the relative width of logic 0 * *
Binary equivalent of the decimal number used to calculate the duty cycle, using the formula: DutyCycle = BZ(5:0) x 0.78125 %
* state at power on initialization
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Control Register CR16 Functions (Address: 0x10)
7 POL 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 6 ORD 5 DIF 4 INV 3 FOR 2 SCL 1 0 Function PREC(1:0) OCK polarity, SCK changes on the rising edge of OCK OCK polarity, SCK changes on the falling edge of OCK Audio I/F data order, the MSB is received first (I2S) Audio I/F data order, the LSB is received first *
*
Audio I/F data alignment, the word is left justified (I2S)(1) * Audio I/F data alignment, the word is right justified (1)
LRCK polarity, when LRCK=0 Left data is received (I2S) (2) * LRCK polarity, when LRCK=1 Left data is received (2)
Audio I/F format, I2S format (first bit is delayed) Audio I/F format, non delayed formats
SCK polarity, SDI and LRCK sampled on the rising edge (I2S) SCK polarity, SDI and LRCK sampled on the falling edge
(3) *
*
Audio I/F data width 16 Audio I/F data width 18 Audio I/F data width 20 Audio I/F data width 24
bit (32 SCK clocks per frame) bit (64 SCK clocks per frame) bit (64 SCK clocks per frame) bit (64 SCK clocks per frame)
*
(1) significant in 18 20 24 bit per word mode only (2) Left Channel data is always received first. (3) First bit delay, in 18 20 24 bit per word mode, is applied only if word is left justified. *: state at power on initialization
Control Register CR17 Functions (Address: 0x11)
7 REN 0 1 0 1 0 1 0 1 X
*: state at power on initialization X: reserved write 0
6 RLM
5 ROI
4 RDL
3
2
1
0 Function Remocon Function disabled Remocon Function enabled Remocon output in transparent mode Remocon output in latched mode Remocon output not inverted Remocon output inverted Remocon detection latch reset by P Remocon detection latch set by internal logic * * * *
X
X
X
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Control Register CR18 Functions (Address: 0x12)
7 6 5 4 3 2 1 SRS 0 Function MD(1:0) 0 0 1 1 0 1 0 1
0 0 1 0 1 X
CFM(1:0)
PU Voice Mode Audio Mode. Tone Only Mode. FM Mode. *
The Master Clock Input for Tone Only and FM Mode is AUXCLK* The Master Clock Input for Tone Only and FM Mode is MCLK The Master Clock Input for Tone Only and FM Mode is OCK
X X 0 1 0 1
*: state at power on initialization X: reserved write 0
Normal Operation Software Reset, all registers are set to their default. Device is in Power Down Device is in Power Up
* *
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Table 1. Tone Generator frequency versus CR13 CR14 register value correspondence table
CR13/14 Value (dec.)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
F1/F2 Tone Frequency (Hz)
0.0 3.9 7.8 11.7 15.6 19.5 23.4 27.3 31.2 35.2 39.1 43.0 46.9 50.8 54.7 58.6 62.5 66.4 70.3 74.2 78.1 82.0 85.9 89.8 93.8 97.7 101.6 105.5 109.4 113.3 117.2 121.1 125.0 128.9 132.8 136.7 140.6 144.5 148.4 152.3 156.2 160.2 164.1 168.0 171.9 175.8 179.7 183.6 187.5 191.4 195.3 199.2 203.1 207.0 210.9 214.8 218.8 222.7 226.6 230.5 234.4 238.3 242.2 246.1
CR13/14 Value (dec.)
64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127
F1/F2 Tone Frequency (Hz)
250.0 257.8 265.6 273.4 281.2 289.1 296.9 304.7 312.5 320.3 328.1 335.9 343.8 351.6 359.4 367.2 375.0 382.8 390.6 398.4 406.2 414.1 421.9 429.7 437.5 445.3 453.1 460.9 468.8 476.6 484.4 492.2 500.0 507.8 515.6 523.4 531.2 539.1 546.9 554.7 562.5 570.3 578.1 585.9 593.8 601.6 609.4 617.2 625.0 632.8 640.6 648.4 656.2 664.1 671.9 679.7 687.5 695.3 703.1 710.9 718.8 726.6 734.4 742.2
CR13/14 Value (dec.)
128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191
F1/F2 Tone Frequency (Hz)
750.0 765.6 781.2 796.9 812.5 828.1 843.8 859.4 875.0 890.6 906.2 921.9 937.5 953.1 968.8 984.4 1000.0 1015.6 1031.2 1046.9 1062.5 1078.1 1093.8 1109.4 1125.0 1140.6 1156.2 1171.9 1187.5 1203.1 1218.8 1234.4 1250.0 1265.6 1281.2 1296.9 1312.5 1328.1 1343.8 1359.4 1375.0 1390.6 1406.2 1421.9 1437.5 1453.1 1468.8 1484.4 1500.0 1515.6 1531.2 1546.9 1562.5 1578.1 1593.8 1609.4 1625.0 1640.6 1656.2 1671.9 1687.5 1703.1 1718.8 1734.4
CR13/14 Value (dec.)
192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255
F1/F2 Tone Frequency (Hz)
1750.0 1781.2 1812.5 1843.8 1875.0 1906.2 1937.5 1968.8 2000.0 2031.2 2062.5 2093.8 2125.0 2156.2 2187.5 2218.8 2250.0 2281.2 2312.5 2343.8 2375.0 2406.2 2437.5 2468.8 2500.0 2531.2 2562.5 2593.8 2625.0 2656.2 2687.5 2718.8 2750.0 2781.2 2812.5 2843.8 2875.0 2906.2 2937.5 2968.8 3000.0 3031.2 3062.5 3093.8 3125.0 3156.2 3187.5 3218.8 3250.0 3281.2 3312.5 3343.8 3375.0 3406.2 3437.5 3468.8 3500.0 3531.2 3562.5 3593.8 3625.0 3656.2 3687.5 3718.8
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STW5094
TIMING DIAGRAM Figure 1. Voice Interface (PCM I/F) Non Delayed Data Timing Mode (*)
tSFM
tRM
tFM
tWMH
MCLK
tHMF
1
tHMF
2
3
4
5
6
tWLM
7
16
17
FS
tDFD tDMD tDMZ
DX
1
2
tSDM
3
tHMD
4
5
6
7
16
DR
1
2
3
4
5
6
7
16
Figure 2. Voice Interface (PCM I/F) Delayed Data Timing Mode (*)
tSFM
tRM
tFM
tWMH
MCLK
tSFM tHMF
1
2
3
4
5
6
tWLM
7
16
17
FS
tDMD
tDMZ
DX
1
2
tSDM
3
tHMD
4
5
6
7
16
DR
1
2
3
4
5
6
7
16
(*) In the case of companded code the timing is applied to 8 bits instead of 16 bits.
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STW5094
TIMING DIAGRAM Figure 3. Voice Interface (PCM I/F) Non Delayed Reverse Data Timing Mode (*)
tSFMR
tRM
tFM
tWMH
MCLK
tHMFR
1
tHMFR
2
3
4
5
6
tWLM
7
16
17
FS
tDFD tDMDR tDMZR
DX
1
2
tSDM
3
tHMD
4
5
6
7
16
DR
1
2
3
4
5
6
7
16
(*) In the case of companded code the timing is applied to 8 bits instead of 16 bits.
Figure 4. Audio Interface (I2S I/F) Timing
tHOCK
OCK
tLOCK
OCK
(polarity inverted)
SCK
SDI
LRCK
tDAI
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Figure 5. Audio Interface (I2S I/F) Formats
I2S Format (delayed), Data word 16 bit, MSB first (default)
16 SCK 16 SCK
LRCK SCK SDI
16 1 MSB 2 13 Left channel 14 15 16 LSB 1 MSB 2 13 Right channel 14 15 16 LSB
Non-delayed Format, SCK polarity inverted, Data word 16 bit, LSB first
16 SCK 16 SCK
LRCK SCK SDI
1 LSB 2 3 Left channel 14 15 16 1 MSB LSB 2 3 Right channel 14 15 16 MSB 1
I2S Format (delayed), Data word 18 bit, Left justified, LSB first
32 SCK 32 SCK
LRCK SCK SDI
X 1 LSB 2 Left channel 17 18 MSB x x 1 LSB 2 Right channel 17 18 MSB x x
Non-delayed Format, Data word 24 bit, Left justified, MSB first, LRCK polarity inverted
32 SCK 32 SCK
LRCK SCK SDI
1 MSB 2 3 Left channel 23 24 LSB x 1 MSB 2 3 Right channel 23 24 LSB x 1
Data word 18 bit, Right justified, MSB first
32 SCK 32 SCK
LRCK SCK SDI
x x x 1 MSB 2 Left channel 18 LSB x x x 1 MSB 2 Right channel 18 LSB x
For the other possible formats see Control Register CR16 description
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Figure 6. Control Interface (I2C I/F) formats
ACK ACK REG n DATA IN STOP ACK ACK REG n DATA IN ACK ACK REG n+m DATA IN m+1 data bytes STOP ACK ACK
WRITE SINGLE BYTE
DEVICE ADDRESS 11100010 START
REG n ADDRESS
WRITE MULTI BYTE
DEVICE ADDRESS 11100010 START
REG n ADDRESS
CURRENT ADDR READ SINGLE BYTE
ACK DEVICE ADDRESS 11100011 START
NO ACK
Current REG DATA OUT STOP ACK ACK ACK NO ACK
CURRENT ADDR READ MULTI BYTE
DEVICE ADDRESS 11100011 START
Current REG DATA OUT
Curr REG+m DATA OUT m+1 data bytes STOP
RANDOM ADDR READ SINGLE BYTE
ACK DEVICE ADDRESS 11100010 START REG n ADDRESS
ACK DEVICE ADDRESS 111000 11 START
ACK REG n DATA OUT
NO ACK
STOP ACK DEVICE ADDRESS 111000 11 REG n DATA OUT ACK ACK REG n+m DATA OUT STOP NO ACK
RANDOM ADDR READ MULTI BYTE
ACK DEVICE ADDRESS 11100010 START REG n ADDRESS
ACK
START
m+1 data bytes
Figure 7. Control Interface (I2C I/F) Timing
SDA
tBUF
tHD (STA)
tLOW
tHD (DAT)
tHIGH
tSU (DAT)
tSU (STA)
tHD (STA)
tSU (STO)
SCL
tR tF
P
S
Sr
P
P = STOP S = START Sr = START repeated
Figure 8. A.C. TESTING INPUT, OUTPUT WAVEFORM INPUT OUTPUT
0.8VCCIO 0.2VCCIO 0.7VCCIO 0.3VCCIO 0.7VCCIO
TEST POINTS
0.3VCCIO
AC Testing: inputs are driven at 0.8VCCIO for a logic "1" and 0.2VCCIO for a logic "0". Timing measurements are made at 0.7VCCIO for a logic "1" and 0.3VCCIO for a logic "0".
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ABSOLUTE MAXIMUM RATINGS
Parameter VCC to GND Voltage at MIC (VCC 3.3V) Current at LSP/N Current at HPR,HPL Current at any digital output Voltage at any digital input (VCCIO 3.3V); limited at 50mA Storage temperature range Value 4.6 VCC +0.5 to GND -0.5 240 100 50 VCCIO + 0.5 to GND -0.5 - 65 to + 150 Unit V V mA mA mA V C
OPERATIVE SUPPLY VOLTAGES
Symbol VCC = VCCA = VCCP VCCIO Min. 2.7 1.8 Max. 3.3 VCC Unit V V
TIMING SPECIFICATIONS (unless otherwise specified, VCCIO = 1.8V to 3.3V,Tamb = -30C to 85C; typical characteristics are specified at VCCIO = 3.0V, Tamb = 25 C; all signals are referenced to GND, see next Note for timing definitions) NOTICE: All timing specifications subject to change. OCK and Audio Interface Signals Timing
Symbol Parameter Test Condition Audio Fs 8kHz or 16kHz Audio Fs 11.025kHz or 22.05kHz Audio Fs 12kHz or 24kHz Audio Fs 32kHz Audio Fs 44.1kHz Audio Fs 48kHz Measured from VIH to VIH Measured from VIL to VIL 35 35 0 20 Min. Typ. 4.096 5.6648 6.144 8.192 11.2896 12.288 Max. Unit MHz MHz MHz MHz MHz MHz ns ns ns
fOCK
Frequency of OCK
(frequency depends on the selected Audio sample rate in CR6)
tHOCK tLOCK tDAI
Period of OCK high Period of OCK low Delay of SCK,SDI and LRCK from OCK active edge
MCLK and AUXCLK Timing
Symbol Parameter Test Condition Frequency is programmable with bits F in CR0 Min. Typ. 512 1.536 2.048 2.560 150 150 30 30 Max. Unit kHz MHz MHz MHz ns ns ns ns
fMCLK
Frequency of MCLK, AUXCLK
tWMH tWML tRM tFM
Period of MCLK, AUXCLK high Period of MCLK, AUXCLK low Rise Time of MCLK, AUXCLK Fall Time of MCLK, AUXCLK
Measured from VIH to VIH Measured from VIL to VIL Measured from VIL to VIH Measured from VIH to VIL
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STW5094
PCM Interface Timing
Symbol tHMF tSFM tDMD tDMZ tDFD Parameter Hold Time MCLK low to FS low Setup Time, FS high to MCLK low Delay Time, MCLK high to data valid Delay Time, MCLK low to DX disabled Delay Time, FS high to data valid Load = 20pF; Applies only if FS rises later than MCLK rising edge in Non Delayed Mode only 20 10 30 30 Load = 20pF 10 20 100 100 Load = 20pF 10 Test Condition Min. 10 30 100 100 100 Typ. Max. Unit ns ns ns ns ns
tSDM tHMD tHMFR tSFMR tDMDR tDMZR tHMDR
Setup Time, DR valid to MCLK receive edge Hold Time, MCLK low to DR invalid Hold Time MCLK High to FS low Setup Time, FS high to MCLK High Delay Time, MCLK low to data valid Delay Time, MCLK High to DX disabled Hold Time, MCLK High to DR invalid
ns ns ns ns ns ns ns
I2C Bus Control Port Timing
Symbol fSCL tHIGH tLOW tR tF tHD:STA tSU:STA tHD:DAT tSU:DAT tSU:STO tBUF
Note: A signal is valid if it is above VIH or below VIL and invalid if it is between VIL and VIH.For the purpose of this specification the following conditions apply (see Fig. 8): a) All input signal are defined as: VIL = 0.2VCCIO, VIH = 0.8VCCIO, tR < 10ns, tF < 10ns. b) Delay times are measured from the inputs signal valid to the output signal valid. c) Setup times are measured from the data input valid to the clock input invalid. d) Hold times are measured from the clock signal valid to the data input invalid.
Parameter Clock Frequency Clock High Time Clock Low Time SDA and SCL Rise Time SDA and SCL Fall Time Start Condition Hold Time Start Condition Setup Time Data Input Hold Time Data Input Setup Time Stop Condition Setup Time Bus Free Time
Test Condition
Min.
Typ.
Max. 400
Unit kHz ns ns
600 1300 1000 300 600 600 0 250 600 1300
ns ns ns ns ns ns ns ns
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STW5094
ELECTRICAL CHARACTERISTICS (unless otherwise specified, VCCIO = 1.8V to 3.3V, Tamb = -30C to 85C; typical characteristic are specified at VCCIO = 3.0V, Tamb = 25C; all signals are referenced to GND) Digital Interfaces (See Figure 8)
Symbol VIL VIH VILREM Parameter Input Low Voltage Input High Voltage Input Low Voltage Test Condition All digital inputs except REMIN All digital inputs except REMIN REMIN input REMIN input All digital outputs, IL = 10A All digital outputs, IL = 2mA All digital outputs, IL = 10A All digital outputs, IL = 2mA Any digital input, GND < VIN < VIL Any digital input, VIH < VIN < VCCIO VCCIO-0.1 VCCIO-0.4 -10 -10 -10 10 10 10 1.4 0.1 0.4 DC AC DC AC 0.7VCCIO 0.8VCCIO 0.5 Min. Typ. Max. 0.3VCCIO 0.2VCCIO Unit V V V V V V V V V V A A A
VIHREM Input High Voltage VOL VOH IIL IIH IOZ Output Low Voltage Output High Voltage Input Low Current Input High Current
Output Current in High impedance DX and CO (Tristate)
Analog Interfaces
Symbol RMBIAS IMIC RMIC RFM RLHP CLHP ROVHP RLLS CLLS ROLS VOSLS Parameter MBIAS Output Resistance MIC Input Leakage MIC Input Resistance FM Input Resistance Single Ended Drivers Load Resistance Single Ended Drivers Load Capacitance Single Ended Drivers Output Resistance Differential Driver Load Resistance Differential Driver Load Capacitance Differential Driver Output Resistance Differential offset Voltage at LSP, LSN Test Condition MBIAS 100mV under VCC GND < VMIC < VCC GND < VMIC < VCC FML, FMR to CAP2 HPL, HPR to GNDP HPL, HPR to GNDP Steady zero PCM code applied to DR; I = 1mA LSP to LSN LSP to LSN Steady zero PCM code applied to DR; I = 1mA Alternating zero PCM code applied to DR maximum receive gain; RL = 50 -50 8 100 50* 1 +50 -100 50 30 30 100 50* 1 Min. Typ. Max. 150 +100 Unit A k k pF nF pF nF mV
* with series resistor
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STW5094
ANALOG INPUT/OUTPUT OPERATIVE RANGES Microphone Input Levels - Absolute levels at MIC1, MIC2
Symbol Parameter 0 dBm0 level Overload level 0 dBm0 level Overload level 0 dBm0 level Overload level Test Condition Transmit gain 0dB Transmit gain 0dB Transmit gain 20dB Transmit gain 20dB Transmit gain 42.5dB Transmit gain 42.5dB Min. Typ. 493 707 2 49 71 200 3.7 5.3 15 Max. Unit mVRMS mVRMS Vpp mVRMS mVRMS mVpp mVRMS mVRMS mVpp
Line Input Level - Absolute levels at MIC3
Symbol Parameter Overload level Test Condition Transmit gain 0dB Min. Typ. 354 1 Max. Unit mVRMS Vpp
FM Input Levels - Absolute levels at FML, FMR
Symbol Parameter Overload level Overload level Test Condition FML, FMR gain 18 dB FML, FMR gain from 6 to -20dB Min. Typ. 177 0.5 707 2 Max. Unit mVRMS Vpp mVRMS Vpp
Power Output Levels - Absolute levels at HPL, HPR
Symbol Parameter Maximum undistorted level Test Condition 30 Load Min. 707 2 Typ. Max. Unit mVRMS Vpp
Power Output Levels - Absolute levels at LSP-LSN (Differentially measured)
Symbol Parameter 0 dBm0 level 0 dBm0 level Maximum undistorted level Test Condition Min. Typ. 984 62.1 1.06 3 Max. Unit mVRMS mVRMS VRMS Vpp
LS gain 0dB LS gain -24dB
8 Load
Tones Levels
Symbol Parameter Tone level at LSP-LSN Tone level at HPL, HPR Test Condition Single tone, sinusoidal waveform, tone gain 0dB, LS gain 0dB Single tone, sinusoidal waveform, tone gain 0dB, HPL, HPR gain -6dB Voice mode, Single tone, sinusoidal waveform, tone gain 0dB Min. Typ. 1.41 4 707 2 -1.64 Max. Unit VRMS Vpp mVRMS Vpp dBFS
Tone level at DX
Note: when 2 tones are enabled the amplitude of f1 is lowered by 5dB and the amplitude of f2 is lowered by 7dB with respect to the amplitude of a single tone.
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VOICE CODEC CHARACTERISTICS (unless otherwise specified, VCC = 2.7V to 3.3V, Tamb = -30C to 85C; FS Frequency = 8kHz; typical characteristics are specified at VCC = 3.0V, Tamb = 25C, MIC1 2 = 0dBm0, DR = -6dBm0 PCM code, f = 1015.625 Hz; all signal are referenced to GND) AMPLITUDE RESPONSE Transmit path
Symbol GXA Parameter Transmit Gain Absolute Accuracy Test Condition Transmit Gain Programmed for minimum. Measure deviation of Digital PCM Code from ideal 0dBm0 PCM code at DX Measure Transmit Gain over the range from Maximum to minimum setting. Calculate the deviation from the programmed gain relative to GXA, i.e. GAXG = G actual - G prog. - GXA Measured relative to GXA. min. gain < GX < Max. gain Measured relative to GXA GX = Minimum gain Digital filter characteristics f = 60 Hz f = 100 Hz f = 200 Hz f = 300 Hz f = 400 Hz to 3000 Hz f = 3400 Hz f = 4000 Hz f = 4600 Hz (*) f = 8000 Hz (*) Digital filter characteristics f = 100 Hz f = 200 Hz to 6000 Hz f = 6800 Hz f = 8000 Hz f = 9200 Hz (*) f = 16000 Hz (*) Sinusoidal Test method. Reference Level = -10 dBm0 VMIC = -40 dBm0 to +3 dBm0 VMIC = -50 dBm0 to -40 dBm0 VMIC = -55 dBm0 to -50 dBm0 -1.5 -0.5 -1.5 0.5 0.5 0.0 -14 -35 -47 dB dB dB dB dB dB -30 -20 -6 0.5 0.5 0.0 -14 -35 -47 dB dB dB dB dB dB dB dB dB Min. -0.5 Typ. Max. 0.5 Unit dB
GXAG
Transmit Gain Variation with programmed gain
-0.5
0.5
dB
GXAT GXAV GXAF8
Transmit Gain Variation with temperature Transmit Gain Variation with supply Transmit Gain Variation with frequency. FS Frequency = 8kHz (VFS=0)
-0.1 -0.1
0.1 0.1
dB dB
-1.5 -0.5 -1.5
GXAF16
Transmit Gain Variation with frequency. FS Frequency = 16kHz (VFS=1)
GXAL
Transmit Gain Variation with signal level
-0.5 -0.5 -1.2
0.5 0.5 1.2
dB dB dB
(*) The limit at frequencies between 4600Hz and 8000Hz lies on a straight line connecting the two frequencies on a linear (dB) scale versus log (Hz) scale.
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STW5094
AMPLITUDE RESPONSE (continued) Receive path
Symbol GRAHPL GRAHPR GRALS Parameter Receive Gain Absolute Accuracy Test Condition Receive gain programmed for maximum Apply -6 dBm0 PCM code to DR Measure HPL, HPR, LSP-LSN Measure HPL, HPR, LSP-LSN Gain over the range from Maximum to minimum setting. Calculate the deviation from the programmed gain relative to GRA, i.e. GRAGLS = G actual - G prog. - GRALS Measured relative to GRA. (HPL, HPR and LSP-LSN) min. gain < GR < Max. gain Measured relative to GRA. (HPL, HPR and LSP-LSN) GR = Maximum Gain Digital filter characteristics f = 60Hz f = 100Hz f = 200 Hz f = 300 Hz f = 400 Hz to 3000 Hz f = 3400 Hz f = 4000 Hz Digital filter characteristics f = 50Hz f = 100 Hz to 3000 Hz f = 3400 Hz f = 4000 Hz Digital filter characteristics f = 100Hz f = 200 Hz to 6000 Hz f = 6800 Hz f = 8000 Hz Sinusoidal Test Method Reference Level = -10 dBm0 DR = -40 dBm0 to -3 dBm0 DR = -50 dBm0 to -40 dBm0 DR = -55 dBm0 to -50 dBm0 -1.5 -0.5 -1.5 0.5 0.5 0.0 -14 dB dB dB dB -1.5 -0.5 -1.5 0.5 0.5 0.0 -14 dB dB dB dB -20 -12 -2 0.5 0.5 0.0 -14 dB dB dB dB dB dB dB Min. -0.5 Typ. Max. 0.5 Unit dB
GRAGHPL Receive Gain Variation with GRAGHPR programmed gain GRAGLS
-0.5
0.5
dB
GRAT
Receive Gain Variation with temperature Receive Gain Variation with Supply Receive Gain Variation with frequency (HPL, HPR and LSP-LSN) FS frequency = 8kHz (VFS=0). High Pass Filter enabled (HPB = 0).
-0.1
0.1
dB
GRAV
-0.1
0.1
dB
GRAF8
-1.5 -0.5 -1.5
Receive Gain Variation with frequency (HPL, HPR and LSP-LSN) FS frequency = 8kHz (VFS=0). High Pass Filter disabled (HPB = 1). GRAF16 Receive Gain Variation with frequency (HPL, HPR and LSP-LSN) FS frequency = 16kHz (VFS=1). GRALHPL GRALHPR GRALLS Receive Gain Variation with signal level (HPL, HPR and LSP-LSN)
-0.5 -0.5 -1.2
0.5 0.5 1.2
dB dB dB
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STW5094
ENVELOPE DELAY DISTORTION WITH FREQUENCY
Symbol DXA DXR Parameter Tx Delay, Absolute Tx Delay, Relative Test Condition f = 1600 Hz f = 500 - 600 Hz f = 600 - 800 Hz f = 800 - 1000 Hz f = 1000 - 1600 Hz f = 1600 - 2600 Hz f = 2600 - 2800 Hz f = 2800 - 3000 Hz f = 1600 Hz f = 500 - 600 Hz f = 600 - 800 Hz f = 800 - 1000 Hz f = 1000 - 1600 Hz f = 1600 - 2600 Hz f = 2600 - 2800 Hz f = 2800 - 3000 Hz Min. Typ. 320 290 180 50 20 55 80 180 280 200 110 50 20 65 100 220 Max. Unit s s s s s s s s s s s s s s s s
DRA DRR
Rx Delay, Absolute Rx Delay, Relative
NOISE
Symbol NXP NRP Parameter Tx Noise, P weighted (up to 35dB) Rx Noise, C-message weighted 8 Load (gain for max. undistorted output level) PSRR, Tx Test Condition V MIC = 0V, DE = 0 Receive PCM code = Zero, SI = 0, RTE = 0 and LSA='0100' (gain -2dB) MIC = 0V, VCC = 3.0 VDC + 50 mVRMS; f = 100Hz to 50kHz PCM Code equals Positive Zero, VCC = 3.0VDC + 50 mVRMS f = 100 Hz - 4 kHz f = 4 kHz - 50 kHz Digital filter characteristics 4600 Hz - 5600 Hz 5600 Hz - 7600 Hz 7600 Hz - 8400 Hz Min. Typ. -75 30 Max. -70 50 Unit dBm0p VRMS
PSRTX
30
dB
PSRRX
PSRR, Rx
30 30 -40 -50 -50
dB dB dB dB dB
SOS
Spurious Out-Band signal at the output
CROSSTALK
Symbol CTX-R Parameter Transmit to Receive Test Condition Transmit Level = 0 dBm0, f = 300 - 3400 Hz DR = Quiet PCM Code Receive Level = -6 dBm0, f = 300 - 3400 Hz MIC = 0V Min. Typ. -100 Max. -65 Unit dB
CTR-X
Receive to Transmit
-80
-65
dB
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STW5094
DISTORTION Receive path
Symbol STDRLS (*) Parameter Signal to Total Distortion (LSP-LSN) (up to 14dB attenuation) 8 Load Typical values are measured with 14dB attenuation. Test Condition Sinusoidal Test Method (measured using linear 300 Hz to 3400 Hz weighting, FS=8kHZ) Level = +3 dBm0 Level = -6 dBm0 Level = -10 dBm0 Level = -20 dBm0 Level = -30 dBm0 Level = -40 dBm0 Level = -45 dBm0 Level = -55 dBm0 Sinusoidal Test Method (measured using linear 300 Hz to 6800 Hz weighting, FS=16kHZ) Level = +3 dBm0 Level = -6 dBm0 Level = -10 dBm0 Level = -20 dBm0 Level = -30 dBm0 Level = -40 dBm0 Level = -45 dBm0 Level = -55 dBm0 Sinusoidal Test Method (measured using linear 300 Hz to 3400 Hz weighting, FS=8kHZ) Level = +3 dBm0 Level = -6 dBm0 Level = -10 dBm0 Level = -20 dBm0 Level = -30 dBm0 Level = -40 dBm0 Level = -45 dBm0 Level = -55 dBm0 Sinusoidal Test Method (measured using linear 300 Hz to 6800 Hz weighting, FS=16kHZ) Level = +3 dBm0 Level = -6 dBm0 Level = -10 dBm0 Level = -20 dBm0 Level = -30 dBm0 Level = -40 dBm0 Level = -45 dBm0 Level = -55 dBm0 Min. Typ. Max. Unit
65 62 54 44 34 29 19
77 70 67 59 49 39 34 24
dB dB dB dB dB dB dB dB
Signal to Total Distortion (LSP-LSN) (up to 14dB attenuation) 8 Load Typical values are measured with 14dB attenuation.
74 67 64 56 46 36 31 21
dB dB dB dB dB dB dB dB
Signal to Total Distortion (HPL, HPR) (up to 14dB attenuation) Typical values are measured with 14dB attenuation
74 67 64 56 46 36 31 21
dB dB dB dB dB dB dB
Signal to Total Distortion (HPL, HPR) (up to 14dB attenuation) Typical values are measured with 14dB attenuation
71 64 61 53 43 33 28 17
dB dB dB dB dB dB dB
(*) The limit curve shall be determined by straight lines joining successive coordinates given in the table.
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STW5094
DISTORTION Transmit path
Symbol STDX (*) Parameter Signal to Total Distortion (up to 35dB gain) FS frequency = 8kHz. Typical values are measured with 30.5dB gain Test Condition Sinusoidal Test Method (measured using linear 300 Hz to 3400 Hz weighting) FSS = 0 Level = +3 dBm0 Level = 0 dBm0 Level = -6 dBm0 Level = -10 dBm0 Level = -20 dBm0 Level = -30 dBm0 Level = -40 dBm0 Level = -45 dBm0 Level = -55 dBm0 Sinusoidal Test Method (measured using linear 300 Hz to 6800 Hz weighting) FSS = 1 Level = +3 dBm0 Level = 0 dBm0 Level = -6 dBm0 Level = -10 dBm0 Level = -20 dBm0 Level = -30 dBm0 Level = -40 dBm0 Level = -45 dBm0 Level = -55 dBm0 Min. Typ. Max. Unit
68 64 59 49 40 30 25 15
75 73 68 64 54 44 34 29 19
dB dB dB dB dB dB dB dB dB
Signal to Total Distortion FS frequency = 16kHz. Typical values are measured with 30.5dB gain
72 70 65 61 51 41 31 26 16
dB dB dB dB dB dB dB dB dB
(*) The limit curve shall be determined by straight lines joining successive coordinates given in the table.
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STW5094
STEREO AUDIO DAC and FM CHARACTERISTICS (Unless otherwise specified, VCC = 2.7V to 3.3V, Tamb = -30C to 85C; typical characteristics are specified at VCC = 3V, Tamb = 25C; OCK = 12.288MHz; Full-Scale Input Sine Waves, 1015.625Hz; Input Sample Rate (Fs) = 48kHz; Input Data = 18Bits; SCK = 3.072 MHz; Measurement Bandwidth is 20Hz to 20kHz, unweighted. Resistive load on HPL, HPR = 30)
Symbol N DYNR THDL Parameter Resolution (*) Dynamic Range Total Harmonic Distortion maximum load Total Harmonic Distortion A-weighted 2Vpp output HPL, HPR gain set to -6dB 30 load 2Vpp output HPL, HPR gain set to -6dB 1k load Measurement Bandwidth 20Hz to 20kHz, Fs= 48kHz.Combined digital and analog filter characteristics. Combined Digital and Analog filter characteristics. Combined Digital and Analog filter characteristics. Combined Digital and Analog filter characteristics. Combined Digital and Analog filter characteristics. Measurement Bandwidth up to 3.45Fs 0.55Fs 50 0 89 92 0.01 0.03 Test Condition Min. Typ. Max. 18 Unit Bits dB %
THD
0.004
%
Deviation from Linear Phase (*)
1
fPB
Passband (*) Passband Ripple (*)
0.45Fs 0.2
kHz dB kHz dB
fSB
StopBand (*) StopBand Attenuation (*)
TSF
Transient suppression filter cutoff frequency Out Of Band Noise Measurement Bandwidth 20kHz to 100kHz. Zero input signal
20 -90 0.4 HPR, HPL unloaded 100 0.2 0.5 11
Hz dBr ms dB dB dB ms
tgd
Group Delay (*) Interchannel Isolation (*) Interchannel Gain Mismatch Gain Error
SUT
Startup Time from Power Up
(*) Valid for I2S input (Audio Mode). NOTE: Fs range: 8kHz - 48kHz.
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STW5094
POWER DISSIPATION (Unless otherwise specified, VCC = 2.7V to 3.3V, Tamb = -30C to 85C, LSP, LSN and HPL, HPR outputs not loaded; typical characteristics are specified at VCC = 3V, Tamb = 25C)
Symbol ICC0 Parameter Power down Current, REMOCON off Power down Current, REMOCON on Test Condition SDA, SCL= VCCIO-0.1V REMOCON function disabled (REN = 0) SDA, SCL= VCCIO-0.1V REMOCON function enabled (REN = 1) REMIN = VILREM or REMIN = VIHREM Fs=8kHz. LSP/N output selected Fs=48kHz. HPL,HPR outputs selected HPL,HPR outputs selected Min. Typ. 0.4 Max. Unit A
ICC0R
2
A
ICC1 ICC2 ICC3
Power Up Current in Voice Codec Mode Power Up Current in Stereo Audio Mode Power Up Current in FM Stereo Mode
4 5 2
6 8 3
mA mA mA
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STW5094
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 1. Stereo DAC performance FFT audio mode (8192 points). Full scale input/output sinewave at 1 kHz (+3dBr) VCC=2.7V, Fs=48kHz, 18 bits input word.
Figure 2. Stereo DAC performance Dynamic range: Noise + THD [dBr] versus signal amplitude [dBm0] VCC=2.7V, Fs=48kHz, 18 bits input word.
Figure 3. Voice RX performance S/(N+THD) [dB] versus signal amplitude [dBm0] with 8 output load VCC=2.7V, Fs=8kHz
Figure 4. Voice TX performance S/(N+THD) versus signal amplitude VCC=2.7V, Fs=8kHz
Digital Audio Filter 10 0 -10 -20 Amplitude [dB] Amplitude [dB] -30 -40 -50 -60 -70 -80 -90 -100 0 0.5 1 1.5 2 Normalized Freq. [Fs] 2.5 3 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 0.05 0.1 0.15
Digital Audio Filter
0.2 0.25 0.3 0.35 Normalized Freq. [Fs]
0.4
0.45
0.5
Figure 5. Digital Audio Filter characteristic Frequency response up to 3.45 Fs
Figure 6. Digital Audio Filter characteristic In band Frequency response
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STW5094
TYPICAL PERFORMANCE CHARACTERISTICS (cont.)
Digital Rx Voice Filter 1 0 -10 0.5 -20 Amplitude [dB] -30 -40 -50 -60 -70 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 20000 Freq. [Hz] -1 0 500 1000 1500 2000 Freq. [Hz] 2500 3000 3500 Amplitude [dB] Digital Rx Voice Filter
0
-0.5
Figure 7. Digital Rx Voice Filter characteristic Frequency response up to 2.5Fs (Fs=8kHz)
Figure 8. Digital Rx Voice Filter characteristic In band Frequency response (Fs=8kHz).
Digital Rx Voice Filter (No High Pass Filt.) 1
0.5 Amplitude [dB]
0
-0.5
-1
0
500
1000
1500 2000 Freq. [Hz]
2500
3000
3500
Figure 9. Digital Rx Voice Filter characteristic In band Frequency response (Fs=8kHz). High Pass filter disabled (HPB=1).
Figure 10. Tx Voice Filter characteristic Full Tx path frequency response (Fs=8kHz).
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STW5094
APPLICATION NOTE
MBIAS 1.8k 750 100nF MIC1P 10F Electret 100nF MIC1N 750 100k 1.8k VDD 3k 1k 10F 1.5k REMIN 100nF MIC2P Electret Call/Answer Button 100nF MIC2N 100k BC546 BZ 33k BC556 32 VDD
REMOUT
To Microprocessor Auxiliary Clock
AUXCLK
Buzzer
MCLK 100nF Line input 10F CAP2 30 Min. 150F HPR 150F HPL SDA SCL SDA SCL MIC3 FS
STW5094
DX DR
PCM Interface
2 I C Bus
0.47F Line In (From FM Stereo Decoder) R L 0.47F FML LRCK SDI LSP SCK 8 Min. LSN OCK SCKT OCLK FMR
2 I S Bus
LRCKT SDO
GNDCM
VCCIO
GNDA
GNDP
VCCA
VCCP
GND
VCC
STA015
MP3 Decoder
VDDIO
100nF
VDD
100nF
100nF
VDD
100nF 10F
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STW5094
mm DIM. MIN. A A1 A2 b D D1 E E1 e f ddd 0.72 0.85 5.85 0.35 5.85 1.01 0.21 0.82 0.40 6.00 4.00 6.00 4.00 0.80 1.00 0.88 1.15 0.10 0.028 0.033 6.15 0.23 0.45 6.15 0.014 0.23 TYP. MAX. 1.20 MIN. 0.040 0.008
inch TYP. MAX. 0.047
OUTLINE AND MECHANICAL DATA
0.032 0.016 0.236 0.157 0.236 0.157 0.031 0.039 0.035 0.045 0.004 0.242 0.018 0.242
Body: 6 x 6 x 1.2mm
TFBGA36 Fine Pitch Ball Grid Array
TFBGA36
7225043
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STW5094
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2003 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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